1. Field of the Invention
The present invention relates to a switched capacitor circuit, and more particularly, to a switched capacitor circuit for use in a voltage controlled oscillator (VCO) that eliminates the clock feedthrough effect thereby preventing a momentary VCO frequency shift and drift when the switched capacitor circuit is switched on or off.
2. Description of the Prior Art
A voltage controlled oscillator (VCO) is commonly used for frequency synthesis in wireless communication circuits. As Welland, et al. state in U.S. Pat. Nos. 6,226,506 and 6,147,567, wireless communication systems typically require frequency synthesis in both the receive path circuitry and the transmit path circuitry.
FIG. 1 shows a VCO circuit with digital tuning according to the prior art. A VCO 10 used in a frequency synthesizer solution is typically based on a resonant structure. Ceramic resonators and LC tank circuits are common examples. While details in the implementation of LC tank oscillators differ, the basic resonant structure includes an inductor 12 connected between a first oscillator node OSC_P and a second oscillator node OSC_N. Connected in parallel with the inductor 12 is a continuously variable capacitor 14 as the varactor and a plurality of discretely variable capacitors 16. The continuously variable capacitor 14 is used for fine-tuning the desired capacitance while the plurality of discretely variable capacitors 16 is used for coarse tuning. The resistive loss of the parallel combination of an inductor and capacitors is compensated by a negative resistance generator 18 to sustain the oscillation.
Each discretely variable capacitor in the plurality of discretely variable capacitors 16 is made up of a switched capacitor circuit 20 and each switched capacitor circuit is controlled by an independent control signal 22. Based on this control signal 22 the switched capacitor circuit 20 can selectively connect or disconnect a capacitance 24 to the resonator of the VCO 10. Different on/off combinations of switched capacitor arrays result in a wider capacitance range of the LC type resonator and hence a wider VCO 10 oscillation frequency coverage.
FIG. 2 shows a single ended switched capacitor circuit 30 according to the prior art. A capacitor 32 is connected between the first oscillator node OSC_P and a node A. A switch element 34 having an NMOS transistor selectively connects node A to the second oscillator node OSC_N that is connected to ground, and the switch element 34 is controlled by a control signal SW. When the switch element 34 is turned on, the capacitance associated with the capacitor 32 is added to the overall capacitance in the VCO 10 resonator. When the switch element 34 is turned off the capacitance looking into the first oscillator node OSC_P is the series combination of the capacitor 32 and the off state capacitance associated with the switch element 34.
FIG. 3 shows another prior art switched capacitor circuit 40, which is a differential implementation without a center switch. Differential implementations have much greater common-mode noise rejection and are widely used in high-speed integrated circuit environments. In the differential without center switch switched capacitor circuit 40, a positive side capacitor 42 is connected between the first oscillator node OSC_P and a node A. A positive side switch element 46 having an NMOS transistor selectively connects node A to ground. A negative side capacitor 44 is connected between the second oscillator node OSC_N and a node B. A negative side switch element 48 having an NMOS transistor selectively connects node B to ground. The two switch elements 46, 48 are controlled by the same control signal SW. When the switch elements are turned on, the capacitance associated with the series combination of the positive and negative side capacitors 42, 44 is added to the overall capacitance in the VCO 10 resonator. When the switch elements 46, 48 are turned off, the differential capacitance between the oscillator nodes OSC_P and OSC_N is the combination of the positive and negative side capacitors 42, 44 and the parasitic capacitance of the off state switch elements in the VCO 10 resonator.
FIG. 4 shows a prior art switched capacitor circuit 60, which is a differential implementation with a center switch. In the differential with center switch switched capacitor circuit 60, a positive side capacitor 62 is connected between the first oscillator node OSC_P and a node A. A positive side switch element 68 having an NMOS transistor selectively connects node A to ground. A negative side capacitor 66 is connected between the second oscillator node OSC_N and a node B. A negative side switch element 70 having an NMOS transistor selectively connects node B to ground. There is also a center switch element 64 having an NMOS transistor used to lower the overall turn-on switch resistance connected between node A and node B. All three switch elements 64, 68, 70 are controlled by the same control signal SW. When the switch elements 64, 68, 70 are turned on, the capacitance associated with the series combination of the positive and negative side capacitors 62, 66 is added to the overall capacitance in the VCO 10 resonator. When the switch elements 64, 68, 70 are turned off, the differential capacitance between the oscillator nodes OSC_P and OSC_N is the combination of the positive and negative side capacitors 62, 66 and the parasitic capacitance of the off state switch elements in the VCO 10 resonator.
FIG. 5 shows a prior art switched capacitor circuit 90, which is a differential implementation with only a center switch. In the differential only center switch switched capacitor circuit 90, a positive side capacitor 92 is connected between the first oscillator node OSC_P and a node A. A negative side capacitor 96 is connected between the second oscillator node OSC_N and a node B. There is a center switch element 94 having an NMOS transistor used to lower the turn-on switch resistance connected between the node A and node B. The switch element 94 is controlled by the control signal SW. When the switch element 94 is turned on, the capacitance associated with the series combination of the positive and negative side capacitors 92, 96 is added to the overall capacitance in the VCO 10 resonator. When the switch element 94 is turned off, the differential capacitance between the oscillator nodes OSC_P and OSC_N is the combination of the positive and negative side capacitors 92, 96 and the parasitic capacitance of the off state switch elements in the VCO 10 resonator.
Regardless of whether the single ended implementation shown in FIG. 2 or the differential implementation shown in FIG. 3, FIG. 4 and FIG. 5 is used, when the switched capacitor circuit 30, 40, 60, or 90 is turned off, a momentary voltage step occurs at node A (and in the case of the differential implementation shown in FIG. 3, FIG. 4 and FIG. 5 also at node B). The momentary voltage step causes an unwanted change in the overall capacitance that is contributed from switches and parasitic diodes of switches, and ultimately, an unwanted change in the VCO 10 frequency. This momentary voltage step could be a voltage drop or rise depending on whether the switch elements are turned off or on with a logic low signal or a logic high signal respectively.
Using the single ended case shown in FIG. 2 as an example, when the switch element 34 is turned off, charge carriers are injected towards the impedances connected to the first terminal and the second terminal of the switch element 34. The injection produces an undesired voltage step across the capacitive impedance and appears as a voltage step at node A. This effect is known as clock feedthrough effect (or simply called “clock feedthrough”) and appears as a feedthrough of the control signal SW from the control terminal of the switch element 34 to the first and second terminals of the switch element 34. When the switch element 34 is turned on, node A is connected to ground so the feedthrough of the control signal SW is of no consequence. However, when the switch element 34 is turned off, the feedthrough of the control signal SW causes a voltage step, in the form of a voltage drop to appear at node A. Because of the dropped voltage at node A, the floating parasitic diode formed by the N+ diffusion of NMOS switch element 34 and the P type substrate in the off state will be slightly forward biased. The voltage level at node A will spike low and then recover to ground potential as the forward biased junction diode formed by the switch element 34 in the off state allows current to flow. The voltage step and recovery at node A changes the capacitance of the VCO 10 resonator and causes an unwanted momentarily shift and drift in the VCO 10 frequency.
When the differential switched capacitor circuits 40, 60 and 90, shown in FIG. 3, FIG. 4, and FIG. 5 respectively, switch off, they with the floating parasitic diodes suffer from the same clock feedthrough problem at node A and at node B. Using the differential with center switch switched capacitor circuit 60 shown in FIG. 4 as an example, the positive side node A has an unwanted voltage step caused by the clock feedthrough of both the positive side switch element 68 and the clock feedthrough of the center switch element 64. Similarly, the negative side node B has an unwanted voltage step caused by the clock feedthrough of both the negative side switch element 70 and the clock feedthrough of the center switch element 64. The voltage step and recovery at node A and node B changes the capacitance of the VCO 10 resonator and causes an unwanted momentary shift and drift in the VCO 10 frequency.